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| a FEATURES FET Input Amplifier 1 pA Typical Input Bias Current Very Low Cost High Speed 80 MHz, -3 dB Bandwidth (G = +1) 80 V/ s Slew Rate (G = +2) Low Noise 11 nV/Hz (f = 100 kHz) 0.6 fA/Hz (f = 100 kHz) Wide Supply Voltage Range 5 V to 24 V Low Offset Voltage, 1 mV Typical Single-Supply and Rail-to-Rail Output High Common-Mode Rejection Ratio -100 dB Low Power 3.3 mA/Amplifier Typical Supply Current No Phase Reversal Small Packaging SOIC-8, SOT-23-8, and SC70 APPLICATIONS Instrumentation Filters Level Shifting Buffering 24 Low Cost, 80 MHz FastFET TM Op Amps AD8033/AD8034 CONNECTION DIAGRAMS SOIC-8 (R) AD8033 SC70 (KS) AD8033 NC 1 -IN 2 +IN 3 8 NC 7 +VS 6 5 VOUT 1 -VS 2 +IN 3 5 +VS VOUT NC 4 -IN -VS 4 SOIC-8 and SOT-23-8 (RT) AD8034 VOUT1 1 -IN1 2 +IN1 3 -VS 4 8 7 6 5 +VS VOUT2 -IN2 +IN2 GENERAL DESCRIPTION G = +10 21 18 G = +5 15 12 GAIN - dB VO = 200mV p-p The AD8033/AD8034 FastFET amplifiers are voltage feedback amplifiers with FET inputs, offering ease of use and excellent performance. The AD8033 is a single amplifier and the AD8034 is a dual amplifier. The AD8033/AD8034 FastFET op amps in ADI's proprietary XFCB process offer significant performance improvements over other low cost FET amps, such as low noise (11 nV/Hz and 0.6 fA/Hz) and high speed (80 MHz bandwidth and 80 V/s slew rate). With a wide supply voltage range from 5 V to 24 V and fully operational on a single supply, the AD8033/AD8034 amplifiers will work in more applications than similarly priced FET input amps. In addition, the AD8033/AD8034 have rail-to-rail outputs for added versatility. Despite their low cost, the amplifiers provide excellent overall performance. They offer high common-mode rejection of -100 dB, low input offset voltage of 2 mV max, and low noise of 11 nV/Hz. The AD8033/AD8034 amplifiers only draw 3.3 mA/amplifier of quiescent current while having the capability of delivering up to 40 mA of load current. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. 9 6 3 G = +2 G = +1 0 -3 G = -1 -6 -9 0.01 1.0 10 FREQUENCY - MHz 100 1000 Figure 1. Small Signal Frequency Response The AD8033 is available in small packages: SOIC-8 and SC70. The AD8034 is also available in small packages: SOIC-8 and SOT-23-8. They are rated to work over the industrial temperature range of -40C to +85C without a premium over commercial grade products. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD8033/AD8034-SPECIFICATIONS (T = 25 C, V = A S 5 V, RL = 1 k , Gain = +2, unless otherwise noted.) Typ 80 30 21 135 135 80 95 225 Max Unit MHz MHz MHz ns ns V/s ns ns Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p -6 V to +6 V Input -3 V to +3 V Input, G = +2 G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 8 V Step fC = 1 MHz, VO = 2 V p-p RL = 500 RL = 1 k RL = 500 RL = 1 k f = 1 MHz, G = +2 f = 100 kHz f = 100 kHz VCM = 0 V TMIN - TMAX Min 65 Input Overdrive Recovery Time Output Overdrive Recovery Time Slew Rate (25% to 75%) Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Distortion Second Harmonic Third Harmonic Crosstalk, Output-to-Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Match Input Offset Voltage Drift Input Bias Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio Specifications subject to change without notice. 55 -82 -85 -70 -81 -86 11 0.7 1 2 3.5 2.5 27 11 dBc dBc dBc dBc dB nV/Hz fA/Hz mV mV mV V/oC pA pA dB G||pF G||pF V V dB V mA pF TMIN - TMAX VO = 3 V 89 4 1.5 50 92 1000||2.3 1000||1.7 -5.0 to +2.2 -5.0 to +5.0 -100 4.95 40 35 VCM = (-3 V to +1.5 V) -89 4.75 30% Overshoot, G = +1, VO = 400 mV p-p 5 VS = 2 V -90 3.3 -100 24 3.5 V mA dB -2- REV. B AD8033/AD8034 SPECIFICATIONS (T = 25 C, V = 5 V, R = 1 k A S L , Gain = +2, unless otherwise noted.) Min Typ 80 32 21 180 200 70 100 Max Unit MHz MHz MHz ns ns V/s ns Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions Input Overdrive Recovery Time Output Overdrive Recovery Time Slew Rate (25% to 75%) Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Distortion Second Harmonic Third Harmonic Crosstalk, Output to Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Match Input Offset Voltage Drift Input Bias Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio Specifications subject to change without notice. G = +1, VO = 0.2 V p-p 70 G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p -3 V to +3 V Input -1.5 V to +1.5 V Input, G = +2 55 G = +2, VO = 4 V Step G = +2, VO = 2 V Step fC = 1 MHz, VO = 2 V p-p RL = 500 RL = 1 k RL = 500 RL = 1 k f = 1 MHz, G = +2 f = 100 kHz f = 100 kHz VCM = 0 V TMIN - TMAX -80 -84 -70 -80 -86 11 0.7 1 2.0 3.5 2.5 30 10 dBc dBc dBc dBc dB nV/Hz fA/Hz mV mV mV V/oC pA pA dB G||pF G||pF V V dB V mA pF TMIN - TMAX VO = 0 V to 3 V 87 4 1 50 92 1000||2.3 1000||1.7 0 to 2.0 0 to 5.0 -100 0.04 to 4.95 30 25 VCM = 1.0 V to 2.5 V RL = 1 k 30% Overshoot, G = +1, VO = 400 mV p-p -80 0.16 to 4.83 5 VS = 1 V -80 3.3 -100 24 3.5 V mA dB REV. B -3- AD8033/AD8034 SPECIFICATIONS Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Input Overdrive Recovery Time Output Overdrive Recovery Time Slew Rate (25% to 75%) Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Distortion Second Harmonic Third Harmonic Crosstalk, Output to Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Match Input Offset Voltage Drift Input Bias Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio Specifications subject to change without notice. (TA = 25 C, VS = 12 V, RL = 1 k , Gain = +2, unless otherwise noted.) Conditions G = +1, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p -13 V to +13 V Input -6.5 V to +6.5 V Input, G = +2 G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 10 V Step fC = 1 MHz, VO = 2 V p-p RL = 500 RL = 1 k RL = 500 RL = 1 k f = 1 MHz, G = +2 f = 100 kHz f = 100 kHz VCM = 0 V TMIN - TMAX Min 65 Typ 80 30 21 100 100 80 90 225 Max Unit MHz MHz MHz ns ns V/s ns ns 55 -80 -82 -70 -82 -86 11 0.7 1 4 2 50 96 1000||2.3 1000||1.7 -12.0 to +9.0 -12.0 to +12.0 -100 11.84 60 35 24 3.5 2.0 3.5 2.5 24 12 dBc dBc dBc dBc dB nV/Hz fA/Hz mV mV mV V/oC pA pA dB G||pF G||pF V V dB V mA pF V mA dB TMIN - TMAX VO = 8 V 88 VCM = 5 V -92 11.52 30% Overshoot; G = +1 5 VS = 2 V -85 3.3 -100 ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2 Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . 26.4 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.4 V Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -4- REV. B AD8033/AD8034 MAXIMUM POWER DISSIPATION MAXIMUM POWER DISSIPATION - W The maximum safe power dissipation in the AD8033/AD8034 packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic that encapsulates the die will locally reach the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8033/AD8034. Exceeding a junction temperature of 175C for an extended period of time can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB ( JA), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as follows TJ = TA + (PD x JA ) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS/2 IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package: 2.0 1.5 SOT-23-8 SOIC-8 1.0 SC70-5 0.5 0.0 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE - C Figure 2. Maximum Power Dissipation vs. Temperature for a Four-Layer Board Airflow will increase heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section. Figure 2 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC-8 (125C/W), SC70 (210C/W), and SOT-23-8 (160C/W) packages on a JEDEC standard 4-layer board. JA values are approximations. OUTPUT SHORT CIRCUIT PD = Quiescent Power + (Total Drive Power - Load Power ) PD = [VS x I S ] + (VS / 2) x (VOUT / RL ) - VOUT / RL 2 [ ] [ ] RMS output voltages should be considered. If RL is referenced to VS-, as in single-supply operation, then the total drive power is VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS /4 for RL to midsupply: PD = (VS x IS ) + (VS / 4) / RL 2 Shorting the output to ground or drawing excessive current for the AD8033/AD8034 will likely cause catastrophic failure. In single-supply operation with RL referenced to VS-, worst case is VOUT = VS /2. ORDERING GUIDE Model AD8033AR AD8033AR-REEL AD8033AR-REEL7 AD8033AKS-REEL AD8033AKS-REEL7 AD8034AR AD8034AR-REEL7 AD8034AR-REEL AD8034ART-REEL AD8034ART -REEL7 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SC70 5-Lead SC70 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOT-23 8-Lead SOT-23 Package Outline R-8 R-8 R-8 KS-5 KS-5 R-8 R-8 R-8 RT-8 RT-8 Branding Information H3B H3B HZA HZA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8033/AD8034 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B -5- AD8033/AD8034-Typical Performance Characteristics Default Conditions: 24 G = +10 21 18 G = +5 15 12 GAIN - dB 6 5 VOUT = 1V p-p 4 3 VOUT = 0.2V p-p 5 V, CL = 5 pF, RL = 1 k , Temperature = 25 C 8 VO = 200mV p-p 7 G = +2 9 6 3 G = +2 G = +1 0 -3 G = -1 -6 -9 0.01 1.0 10 FREQUENCY - MHz 100 1000 1 0 VOUT = 2V p-p 0.1 1 10 FREQUENCY - MHz 100 2 VOUT = 4V p-p TPC 1. Small Signal Frequency Response for Various Gains TPC 4. Frequency Response for Various Output Amplitudes (See Test Circuit 2) 1 VS = +5V 0 -1 GAIN - dB GAIN - dB 8 7 VS = 5V 6 12V 5 4 3 VS = 5V VS = +5V -2 -3 -4 GAIN - dB VS = 2 -5 G = +1 VO = 200mV p-p -6 0.1 1 10 FREQUENCY - MHz 100 1 0 G = +2 VO = 200mV p-p 0.1 1 VS = 12V 10 FREQUENCY - MHz 100 TPC 2. Small Signal Frequency Response for Various Supplies (See Test Circuit 1) TPC 5. Small Signal Frequency Response for Various Supplies (See Test Circuit 2) 2 G = +1 1 VOUT = 2V p-p 0 -1 GAIN - dB 7 VS = 6 12V VS = 12V 5 VS = 5V VS = +5V VS = 5V GAIN - dB VS = +5V -2 -3 -4 -5 -6 0.1 4 3 2 1 1 10 FREQUENCY - MHz 100 0 0.1 G = +2 VO = 2V p-p 1 10 FREQUENCY - MHz 100 TPC 3. Large Signal Frequency Response for Various Supplies (See Test Circuit 1) TPC 6. Large Signal Frequency Response for Various Supplies (See Test Circuit 2) -6- REV. B AD8033/AD8034 8 VO = 200mV p-p G = +1 CL = 100pF RSNUB = 25 GAIN - dB 10 CL = 100pF 9 8 7 6 5 4 3 G = +2 2 1 VO = 200mV p-p CL = 2pF CL = 33pF CL = 51pF CL = 100pF 6 4 GAIN - dB 2 0 CL = 33pF -2 CL = 2pF -4 -6 0.1 1 10 FREQUENCY - MHz 100 0 0.1 1 10 FREQUENCY - MHz 100 TPC 7. Small Signal Frequency Response for Various CLOAD (See Test Circuit 1) TPC 10. Small Signal Frequency Response for Various CLOAD (See Test Circuit 2) 9 8 7 6 GAIN - dB GAIN - dB 8 CF = 0pF CF = 1pF 7 6 5 VO = 200mV p-p G = +2 RL = 1k 5 4 3 2 1 0 VO = 200mV p-p RF = 3k G = +2 0.1 1 CF = 1.5pF CF = 2pF RL = 500 4 3 2 1 0 0.1 10 FREQUENCY - MHz 100 1 10 FREQUENCY - MHz 100 TPC 8. Small Signal Frequency Response for Various RF/CF (See Test Circuit 2) TPC 11. Small Signal Frequency Response for Various RLOAD (See Test Circuit 2) 100 100 VO = 200mV p-p 180 VS = 12V 150 80 10 G = +2 1 40 PHASE 20 90 G = +1 0.1 60 0 30 0.01 100 1k 10k 100k FREQUENCY - Hz 1M 10M 100M -20 100 1k 10k 100k 1M FREQUENCY - Hz 10M 0 100M TPC 9. Output Impedance vs. Frequency (See Test Circuits 4 and 7) TPC 12. Open-Loop Response REV. B -7- PHASE - Degrees 60 IMPEDANCE - GAIN 120 GAIN - dB AD8033/AD8034 -40 G = +2 -50 -60 DISTORTION - dBc -40 HD3 RL = 500 -50 -60 DISTORTION - dBc -70 -80 -90 -100 -110 -120 0.1 HD2 RL = 1k 1 FREQUENCY - MHz 5 HD2 RL = 500 HD3 RL = 1k -70 HD2 G = +1 -80 HD3 G = +2 -90 HD2 G = +2 -100 -110 HD3 G = +1 -120 0.1 1 FREQUENCY - MHz 5 TPC 13. Harmonic Distortion vs. Frequency for Various Loads (See Test Circuit 2) TPC 16. Harmonic Distortion vs. Frequency for Various Gains -40 G = +2 -50 -60 HD3 VS = 5V -20 -30 -40 HD3 VO = 10V p-p HD3 VO = 20V p-p HD2 VO = 20V p-p DISTORTION - dBc -50 -70 -80 HD2 VS = 5V -90 -100 -110 -120 0.1 HD2 VS = 24V 1 FREQUENCY - MHz 5 HD3 VS = 24V DISTORTION - dBc -60 -70 -80 -90 -100 -110 -120 0.1 HD2 VO = 10V p-p HD3 VO = 2V p-p HD2 VO = 2V p-p 1 FREQUENCY - MHz 5 TPC 14. Harmonic Distortion vs. Frequency for Various Supply Voltages (See Test Circuit 2) TPC 17. Harmonic Distortion vs. Frequency for Various Amplitudes (See Test Circuit 2), VS = 24 V 1000 80 VS = +5V POSITIVE SIDE 70 60 50 40 30 20 VS = 10 5V POSITIVE SIDE VS = 5V NEGATIVE SIDE PERCENT OVERSHOOT VS = +5V NEGATIVE SIDE NOISE - nV/ Hz 100 10 10 100 1k 10k 100k 1M 10M 100M FREQUENCY - Hz 0 10 30 50 70 CAP LOAD - pF 90 110 TPC 15. Voltage Noise TPC 18. Capacitive Load vs. Percent Overshoot G = +1 (See Test Circuit 1) -8- REV. B AD8033/AD8034 G = +1 38pF 15pF G = +1 25mV/DIV 20ns/DIV 80mV/DIV 80ns/DIV TPC 19. Small Signal Transient Response 5 V (See Test Circuit 1) TPC 22. Small Signal Transient Response 5 V (See Test Circuit 1) VO = 20V p-p VO = 20V p-p VO = 8V p-p VO = 2V p-p VO = 8V p-p VO = 2V p-p 3V/DIV 320ns/DIV 3V/DIV 320ns/DIV TPC 20. Large Signal Transient Response G = +1 (See Test Circuit 1) TPC 23. Large Signal Transient Response G = +2 (See Test Circuit 2) G = -1 VIN VOUT G = +1 VOUT VIN 1.5V/DIV 350ns/DIV 1.5V/DIV 350ns/DIV TPC 21. Output Overdrive Recovery (See Test Circuit 3) TPC 24. Input Overdrive Recovery (See Test Circuit 1) REV. B -9- AD8033/AD8034 VIN = 1V VIN = 1V VOUT - 2VIN +0.1% +0.1% -0.1% t=0 t=0 VOUT - 2VIN -0.1% 2mV/DIV 1.5 s/DIV 2mV/DIV 20ns/DIV TPC 25. Long-Term Settling Time TPC 28. 0.1% Short-Term Settling Time 0 -5 QUIESCENT CURRENT - mA 7.0 6.9 6.8 VS = 12V -10 -Ib -15 Ib - pA 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 VS = +5V VS = 5V -20 +Ib -25 -30 -35 -40 20 25 30 35 40 45 50 55 60 65 TEMPERATURE - C 70 75 80 85 5.9 -40 -20 0 20 40 TEMPERATURE - C 60 80 TPC 26. Ib vs. Temperature TPC 29. Quiescent Supply Current vs. Temperature for Various Supply Voltages 42 36 30 BJT INPUT RANGE 4.0 -Ib +Ib 3.5 VS = NORMALIZED OFFSET - mV 3.0 2.5 2.0 1.5 1.0 VS = .50 0 -.50 5V VS = +5V 12V Ib = A 24 18 12 6 0 10 5 0 -5 -10 -15 -20 -25 -30 -12 -10 FET INPUT RANGE +Ib Ib - pA -Ib -8 -6 -4 -2 0 2 4 6 8 10 12 -1.0 -14 -12 -10 -8 COMMON-MODE VOLTAGE - V -6 -4 -2 0 2 4 6 8 COMMON-MODE VOLTAGE - V 10 12 14 TPC 27. Input Bias Current vs. Common-Mode Voltage Range TPC 30. Input Offset Voltage vs. CommonMode Voltage -10- REV. B AD8033/AD8034 -20 105 100 -30 95 OPEN-LOOP GAIN - dB -40 CMRR - dB 90 85 80 75 70 RL = 500 RL = 1k RL = 2k -50 -60 -70 65 -80 0.1 1 10 FREQUENCY - MHz 50 60 -12 -10 -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE - V 6 8 10 12 TPC 31. CMRR vs. Frequency (See Test Circuit 7) TPC 34. Open-Loop Gain vs. Output Voltage for Various RLOAD 1.0 -40 0.8 OUTPUT SATURATION - V -50 SOT-23 A/B CROSSTALK - dB VCC VOH 0.6 -60 SOIC A/B -70 SOT-23 B/A SOIC B/A -80 0.4 VOL VEE 0.2 -90 0 0 5 10 15 ILOAD - mA 20 25 30 -100 0.1 1 FREQUENCY - MHz 10 50 TPC 32. Output Saturation Voltage vs. Load Current TPC 35. Crosstalk (See Test Circuit 9) 0 -10 -20 -30 PSRR - dB 180 150 -40 -50 -60 +PSRR -70 -80 -90 FREQUENCY -PSRR 120 90 60 30 -100 0.0001 0 0.001 0.01 0.1 1 FREQUENCY - MHz 10 100 -1.5 -1.0 -0.5 0 VOS - mV 0.5 1.0 1.5 TPC 33. PSRR vs. Frequency (See Test Circuits 6 and 8) TPC 36. Initial Offset REV. B -11- AD8033/AD8034 VOUT VOUT 1.2V/DIV VIN 1 s/DIV 1.2V/DIV VIN 1 s/DIV TPC 37. G = +1 Response VS = 5 V TPC 38. G = +2 Response VS = 5 V Test Circuits 1k CF 1k RF VCC 1F + 10nF RSNUB VIN 49.9 976 VOUT CLOAD 49.9 VIN 499 49.9 VCC 1F + 10nF RSNUB 976 VOUT CLOAD 49.9 AD8033/AD8034 10nF AD8033/AD8034 10nF + 1F VEE + 1F VEE Test Circuit 1. G = +1 Test Circuit 2. G = +2 VIN 1k 1k VCC 1F + 10nF 976 VOUT VCC 1F + 10nF 1k 1k VCC 1F + 10nF AD8033/AD8034 499 10nF 49.9 AD8033/AD8034 10nF VSINE 0.2V p-p + - AD8033/AD8034 10nF VSINE 0.2V p-p + 1F VEE + - + 1F VEE + 1F VEE Test Circuit 3. G = -1 Test Circuit 4. Output Impedance G = +1 Test Circuit 5. Output Impedance G = +2 -12- REV. B AD8033/AD8034 1V p-p + VCC AC 49.9 - VCC VCC 1F + 10nF VOUT VOUT AD8033/AD8034 10nF 1V p-p VEE - AD8033/AD8034 + + 1F VEE VEE AC 49.9 Test Circuit 6. Positive PSRR Test Circuit 8. Negative PSRR 1k 1k 1k 1k VEE - TO PORT 1 499 + 50 - +B VCC VEE + TO PORT 2 A 499 VCC VIN 49.9 1F + 10nF 976 1k VOUT 49.9 1k VIN AD8033/AD8034 1k 10nF + 1F VEE 1k - VCC 1k 1k Test Circuit 7. CMRR Test Circuit 9. Crosstalk REV. B -13- AD8033/AD8034 THEORY OF OPERATION The incorporation of JFET devices into Analog Devices' high voltage XFCB process has given the performance ability to design the AD8033/AD8034. The AD8033/AD8034 are voltage feedback rail-to-rail output amplifiers with FET inputs and a bipolar-enhanced common-mode input range. The use of JFET devices in high speed amplifiers extends the application space into both low input bias current as well as low distortion high bandwidth areas. Using N-channel JFETs and a folded cascade input topology, the common-mode input level operates from 0.2 V below the negative rail to within 3.0 V of the positive rail. Cascading of the input stage ensures low input bias current over the entire common-mode range as well as CMRR and PSRR specifications that are above 90 dB. Additionally, long-term settling issues that normally occur with high supply voltages are minimized as a result of the cascading. Output Stage Drive and Capacitive Load Drive bipolar pair Q25 and Q27. With this configuration, the inputs can be driven beyond the positive supply rail without any phase inversion (see Figure 3). As a result of entering the bipolar mode of operation, an offset and input bias current shift will occur. See TPCs 27 and 30. After re-entering the JFET common-mode range, the amplifier will recover in approximately 100 ns (refer to TPC 24 for input overload behavior). Above and below the supply rails, ESD protection diodes activate, resulting in an exponentially increasing input bias current. If the inputs are to be driven well beyond the rails, series input resistance should be included to limit the input bias current to less than 10 mA. Input Impedance The common emitter output stage adds rail-to-rail output performance and is compensated to drive 35 pF (30% overshoot G = +1). Additional capacitance can be driven if a small snub resistor is put in series with the capacitive load, effectively decoupling the load from the output stage, as shown in TPC 7. The output stage can source and sink 20 mA of current within 500 mV of the supply rails and 1 mA within 100 mV of the supply rails. Input Overdrive The input capacitance of the AD8033/AD8034 will form a pole with the feedback network, resulting in peaking and ringing in the overall response. The equivalent impedance of the feedback network should be kept small enough to ensure that the parasitic pole falls well beyond the -3 dB bandwidth of the gain configuration being used. If larger impedance values are desired, the amplifier can be compensated by placing a small capacitor in parallel with the feedback resistor. TPC 8 shows the improvement in frequency response by including a small feedback capacitor with high feedback resistance values. Thermal Considerations An additional feature of the AD8033/AD8034 is a bipolar input pair that adds rail-to-rail common-mode input performance specifically for applications that cannot tolerate phase inversion problems. Under normal common-mode operation, the bipolar input pair is kept reversed, maintaining Ib at less than 1 pA. When the input common mode comes within 3.0 V of the positive supply rail, I1 turns off and I4 turns on, supplying tail current to the +VS Because the AD8034 operates at up to 12 V supplies in the small SOT-23-8 package (160C/W), power dissipation can easily exceed package limitations, resulting in permanent shifts in device characteristics and even failure. Likewise, high supply voltages can cause an increase in junction temperature even with light loads, resulting in an input bias current and offset drift penalty. The input bias current will double for every 10C shown in TPC 26. Refer to the Maximum Power Dissipation section for an estimation of die temperature based on load and supply voltage. R2 I2 R3 V2 + V4 - + - Q4 Q13 Q1 Q14 VTH Q6 Q7 R14 -IN J1 D4 Q25 Q27 D5 Q11 Q9 J2 +IN VCC VOUT Q29 Q28 I1 -VS I4 R7 I3 R8 Figure 3. Simplified AD8033/AD8034 Input Stage -14- REV. B AD8033/AD8034 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS Bypassing Power supply pins are actually inputs, and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering a majority of the noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.01 F or 0.001 F (X7R or NPO) chip capacitors are critical and should be placed as close as possible to the amplifier package. Larger chip capacitors, such as the 0.1 F capacitor, can be shared among a few closely spaced active components in the same signal path. The 10 F tantalum capacitor is less critical for high frequency bypassing, and in most cases, only one per board is needed at the supply inputs. Grounding leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above, and below using a multilayer board. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring will help to reduce the absorption. Also, low absorption materials such as Teflon(R) or ceramic may be necessary in some instances. Input Capacitance A ground plane layer is important in densely packed PC boards in order to spread the current, thereby minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances, and thus the high frequency impedance of the path. High speed currents in an inductive ground return will create unwanted voltage noise. The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors that are intended to be effective at lower frequencies, the current return path distance is less critical. Leakage Currents Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifiers' gain and causing peaking of the overall response or even oscillations if severe enough. It is recommended that the external passive components that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a distance of at least 0.05 mm from the input pins on all layers of the board. APPLICATIONS High Speed Peak Detector The low input bias current and high bandwidth of the AD8033/ AD8034 make the parts ideal for a fast settling, low leakage peak detector. The classic fast-low leakage topology with a diode in the output is limited to 1.4 V p-p max in the case of the AD8033/AD8034 because of the protection diodes across the inputs, as depicted in Figure 4. Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias currents of the AD8033/AD8034. Any voltage differential between the inputs and nearby runs will set up leakage currents through the PC board insulator, for example, 1 V/100 G = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). To significantly reduce leakages, put a guard ring (shield) around the inputs and input AD8033/ AD8034 VIN ~1.4V p-p MAX VOUT Figure 4. High Speed Peak Detector with Limited Input Range REV. B -15- AD8033/AD8034 Using the AD8033/AD8034, a unity gain peak detector can be constructed that will capture a 300 ns pulse while still taking advantage of the AD8033/AD8034's low input bias current and wide common-mode input range, as shown in Figure 5. Using two amplifiers, the difference between the peak and the current input level is forced across R2 instead of either amplifier's input pins. In the event of a rising pulse, the first amplifier compensates for the drop across D2 and D3, forcing the voltage at Node 3 equal to Node 1. D1 is off and the voltage drop across R2 is zero. Capacitor C3 speeds up the loop by providing the charge required by the first amplifier's input capacitance, helping to maintain a minimal voltage drop across R2 in the sampling mode. A negative going edge results in D2 and D3 turning off and D1 turning on, closing the loop around the first amplifier and forcing VOUT - VIN across R2. R4 makes the voltage across D2 zero, minimizing leakage current and kickback from D3 from affecting the voltage across C2. The rate of the incoming edge must be limited so that the output of the first amplifier does not overshoot the peak value of VIN before the second amplifier's output can provide negative feedback at the first amplifier's summing junction. This is accomplished with the combination of R1 and C1, which allows the voltage at Node 1 to settle to 0.1% of VIN in 270 ns. The selection of C2 and R3 is made by considering droop rate, settling time, and kickback. R3 prevents overshoot from occurring at Node 3. The time constants of R1, C1 and R3, C2 are roughly equal to achieve the best performance. Slower time constants can be selected by increasing C2 to minimize droop rate and kickback at the cost of increased settling time. R1 and C1 should also be increased to match, reducing the incoming pulse's effect on kickback. C3 10pF INPUT OUTPUT 1.00V/DIV 100nS/DIV Figure 6. Peak Detector Response 4 V 300 ns Pulse Figure 6 shows the peak detector in Figure 5 capturing a 300 ns 4 V pulse with 10 mV of kickback and a droop rate of 5 V/s. For larger peak-peak pulses, the time constants of R1, C1 and R3, C3 should be increased to reduce overshoot. The best droop rate will occur by isolating parasitic resistances from Node 3. This can be accomplished using a guard band connected to the output of the second amplifier that surrounds its summing junction (Node 3). Increasing both time constants by a factor of 3 permits a larger peak pulse to be captured and increases the output accuracy. R2 1k LS4148 D1 C4 4.7pF +VS R1 1k R5 49.9 1/2 D3 LS4148 -VS C1 39pF/ 120pF D2 LS4148 C2 R3 200 180pF/560pF R4 6k 1/2 +VS AD8034 -VS VOUT AD8034 VIN Figure 5. High Speed Unity Gain Peak Detector Using AD8034 -16- REV. B AD8033/AD8034 0 INPUT -10 -20 OUTPUT -30 REF LEVEL - dB -40 -50 -60 -70 -80 1.00V/DIV 200nS/DIV -90 -100 10k Figure 7. Peak Detector Response 5 V 1 s Pulse Figure 7 shows a 5 V peak pulse being captured in 1 s with less than 1 mV of kickback. With this selection of time constants, up to a 20 V peak pulse can be captured with no overshoot. Active Filters 100k 1M FREQUENCY - Hz 10M Figure 9. Four-Pole Cascade Sallen-Key Filter Response The response of an active filter varies greatly depending on the performance of the active device. Open-loop bandwidth and gain, along with the order of the filter, will determine stop-band attenuation as well as the maximum cutoff frequency, while input capacitance can set a limit on which passive components are used. Topologies for active filters are varied, and some are more dependent on the performance of the active device than others. The Sallen-Key topology is the least dependent on the active device, requiring that the bandwidth be flat to beyond the stopband frequency since it is used simply as a gain block. In the case of high Q filter stages, the peaking must not exceed the open-loop bandwidth and linear input range of the amplifier. Using an AD8033/AD8034, a four-pole cascaded Sallen-Key filter can be constructed with fC = 1 MHz and over 80 dB of stop-band attenuation, as shown in Figure 8. C3 33pF R1 4.22k R5 49.9 R2 6.49k 1/2 The common-mode input capacitance should be considered in the component selection. Filter cutoff frequencies can be increased beyond 1 MHz using the AD8033/AD8034, but limited open-loop gain and input impedance begin to interfere with the higher Q stages. This can cause early roll-off of the overall response. Additionally, the stop-band attenuation will decrease with decreasing open-loop gain. Keeping these limitations in mind, a two-pole Sallen-Key Butterworth filter with fC = 4 MHz can be constructed that has a relatively low Q of 0.707 while still maintaining 15 dB of attenuation an octave above fC and 35 dB of stop-band attenuation. The filter and response are shown in Figures 10 and 11, respectively. C3 22pF +VS R2 2.49k C1 10pF +VS VIN R5 49.9 R1 2.49k AD8033 -VS VOUT VIN AD8034 -VS C1 27pF Figure 10. Two-Pole Butterworth Active Filter 5 0 C4 82pF R4 4.99k R3 4.99k C2 10pF 1/2 -5 +VS -10 GAIN - dB AD8034 -VS VOUT -15 -20 -25 -30 Figure 8. Four-Pole Cascade Sallen-Key Filter -35 -40 -45 100k Component values are selected using a normalized cascaded two-stage Butterworth filter table and Sallen-Key two-pole active filter equations. The overall frequency response is shown in Figure 9. 1M FREQUENCY - Hz 10M 100M Figure 11. Two-Pole Butterworth Active Filter Response REV. B -17- AD8033/AD8034 Wideband Photodiode Preamp Figure 12 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is VOUT I x RF = PHOTO 1 + sCF RF is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects that will add to the output noise. Integrating the square of the output voltage noise spectral density over frequency and then taking the square root results in the total rms output noise of the preamp. CF where IPHOTO is the output current of the photodiode, and the parallel combination of RF and CF sets the signal bandwidth. The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier's summing junction, including CS and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier's loop transmission that can result in peaking and instability. Adding CF creates a zero in the loop transmission that compensates for the pole's effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45 phase margin (f(45)) is defined by the expression RF RSH = 1011 IPHOTO CS CD CM CM VO VB CF + CS RF f( 45 ) = fCR 2 x RF x CS Figure 12. Wideband Photodiode Preamp fCR is the amplifier crossover frequency. RF is the feedback resistor. CS is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). The value of CF that produces f(45) can be shown to be CF = CS 2 x RF x fCR VOLTAGE NOISE - nV/ Hz f1 = 1 2 RF (CF + CS + CM + 2CD) 1 2 RFCF f2 = f3 = fCR (CS + CM + 2CD + CF ) /CF RF NOISE The frequency response in this case will show about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half will result in a flat frequency response, with about 5% transient overshoot. The preamp's output noise over frequency is shown in Figure 13. The pole in the loop transmission translates to a zero in the amplifier's noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission zero introduced by CF limits the amplification. The noise gain's bandwidth extends past the preamp signal bandwidth and f2 f1 VEN VEN (CF + CS + CM + 2CD) /CF f3 NOISE DUE TO AMPLIFIER FREQUENCY - Hz Figure 13. Photodiode Voltage Noise Contributions -18- REV. B AD8033/AD8034 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8-Lead Small Outline Transistor Package [SOT-23] (RT-8) Dimensions shown in millimeters 2.90 BSC 5.00 (0.1968) 4.80 (0.1890) 8 8 5 4 7 6 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 1.60 BSC 1 2 3 4 2.80 BSC PIN 1 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075) 0.50 (0.0196) 0.25 (0.0099) 0.65 BSC 45 1.30 1.15 0.90 1.95 BSC 0.51 (0.0201) 0.33 (0.0130) 1.27 (0.0500) 0.41 (0.0160) 0.15 MAX 0.38 0.22 1.45 MAX 0.22 0.08 10 0 COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178BA 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters 2.00 BSC 5 4 1.25 BSC 1 2 3 2.10 BSC PIN 1 1.00 0.90 0.70 0.65 BSC 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY SEATING PLANE 0.46 0.36 0.26 0.10 MAX COMPLIANT TO JEDEC STANDARDS MO-203AA REV. B -19- AD8033/AD8034 Revision History Location 2/03--Data Sheet changed from REV. A to REV. B. Page Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Replaced TPC 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to TPC 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Test Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8/02--Data Sheet changed from REV. 0 to REV. A. C02924-0-2/03(B) PRINTED IN U.S.A. Changes to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added AD8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal VOUT = 2 V p-p deleted from Default Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Added SOIC-8 (R) and SC70 (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to GENERAL DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to MAXIMUM POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Change to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Change to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Change to TPC 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 New TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 New TPC 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 New TPC 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 New TPC 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 New Test Circuit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SC70 (KS) package added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 -20- REV. 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Price & Availability of AD8034AR
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